Chip design challenge open to students and faculty

Submitted by Sonja Bickford
Phone: 455-2013
12/03/04

The Semiconductor Research Corporation (SRC) and the Semiconductor Industry Association (SIA) announce their co-sponsorship of a contest open to North American university students and faculty to create novel, low-power SoC designs that demonstrate the value of greater systems integration in IC design.

Total prizes amounting to $75,000 will be awarded to winning submissions. Finalists will have an opportunity to have their designs fabricated by MOSIS in an advanced 180-nm CMOS technology. Major partner companies providing funding for the fabrication phase of the challenge include: AMD, AMI, Analog Devices, Cadence, Freescale, IBM, Intel, National Semiconductor, and Texas Instruments.

The contest will be conducted in two phases, with prizes awarded to the top three contestants in each phase. In Phase One, contestants will submit chip designs using novel architectures or subsystems that exploit the advantages of greater systems integration. Cash prizes of $7,000, $5,000, and $3,000 will be awarded for first, second, and third place winners. In Phase Two, the top five entries from Phase One will complete their layouts and submit their designs for fabrication on a 180-nm, mixed-signal CMOS process at MOSIS.

The top winners will be awarded cash prizes of $25,000, $15,000, and $10,000 for first, second, and third places. All monetary prizes will go to the winning teams’ Electrical Engineering departments to help further studies in this important area. For full information on the contest, go to www.src.org/SoC_contest/SoC_wp.asp.